Comments on Profile Post by SoupRKnowva

Next step, 32x16-bit Block RAM.

lol ill pass, id rather just instantiate one of those in Verilog :P

Verilog is all kinds of awesome.

i do love me some Verilog <3 My research has got me writing all this SystemC for testbenches, which are important too, but man, i just want to get back to the Verilog

A lot of folks use direct C++ more over SystemC. Cuz it's kind of free. Particularly for system model test vectors (given to the ASIC dudes). For HDL sanity test benches, many folks stay in the Verilog realm. SystemC is a good skill though.

C++ is more of a pain than SystemC though given some of the data type stuff is taken care off.