Comments on Profile Post by SoupRKnowva

We spent the last several days doing logic synthesis and bringing critical paths down from >3ns to 2.2ns. Anything further would require dramatic architectural changes we don't have time for. Pretty proud of what me and my partner accomplished on this beast.

Now we just need to finish getting it through the backend tools and laid out in silicon so we can get it turned in

Critical path: 3ns+ -> 2.2ns. Is real time all that's typically considered now? Was wondering about cycles, and what clock speed you used to get that.

Had an interview once where I had to provide the total clock cycles for a loop in Z80 assembly. Missed it by 1 cycle because the positive branch of an if took +1 cycle than the negative.

Man that was a long time ago.

when I say critical path I mean in the heardware for a single cycle, so the critical path is what determines your cycle time and therefor the clockspeed you can run the chip at. So we took it from passing timing at ~300MHZ to doing so at 450MHz with some reasonably minor changes to the architecture. Getting the cycle time down further would require much more significant changes we dont have time for.